1. Field
The subject matter discloses herein relates to devices and methods of processing data received from a transmission medium. In particular, the subject matter disclosed herein relates to processing signals received from a communication channel in the presence of noise and distortion.
2. Information
To recover information from a signal received from noisy communication channel with distortion, receivers typically employ filtering and equalization techniques to enable reliable detection of the information. Decreases in the cost of digital circuitry have enabled the cost effective use of adaptive digital filtering and equalization techniques that can optimally “tune” a filter according to the specific characteristics of a noisy communication channel with distortion.
FIG. 1 shows a conventional digital filter 10 employing a finite impulse response (FIR) configuration. An analog input signal 12 is received at an analog to digital converter (ADC) 14 to provide a digital signal at discrete sample intervals. The analog input signal 12 may be transmitting encoded symbols representing information in a noisy communication channel with distortion. The ADC 14 may sample the analog input signal at discrete sample intervals corresponding with an inter-symbol temporally spacing, or fractions thereof.
In a feed forward portion of the digital filter 10, on each discrete sample interval, the digital signal from the present discrete sample interval is provided to a multiplication circuit 20 to be scaled by coefficient c0, and signal taps at two previous sample intervals (i.e., the digital samples from the two previous discrete sample intervals delayed by delay circuits 16) are provided to multiplication circuits 20 to be scaled by coefficients c2 and C4, respectively. The outputs of the three multiplication circuits are then additively combined at a summing circuit 22 as feed forward components of an equalized signal.
The coefficients c0, c2 and C4 are typically updated to approximate a least mean square error (LMS) filter for the particular FIR filter configuration. A limiting circuit 30 may provide a bi-level detection of symbols from the equalized signal output of the summing circuit 22, and differencing circuit 28 provides a difference between the filtered output and the detected symbol as an “error.” A limiting circuit 26 provides a sign of the error to each of three multiplication circuits 25 for updating the coefficients c0, c2 and C4. Each of the multiplication circuits 25 multiplies the sign of the error with the sign of a corresponding signal tap of the digital signal (as detected at a limiting circuit 18) and a sample and hold circuit 24 generates an updated coefficient.
In a feedback portion of the digital filter 10, an output data signal 38 from the detector circuit 30 is tapped at delay circuit 32 and combined with the sign of the error generated by limiting circuit 26. The result is integrated at sample and hold circuit 34 to generate a feedback coefficient. A multiplication circuit 31 then scales the output of delay circuit 32 by the feedback coefficient to provide a feedback component of the equalized signal output at summing circuit 22.
FIG. 2 shows a conventional implementation of a feed back portion of the digital filter 10. An equalized signal 42 is combined with a scaled output of flip-flop circuit 46 (i.e., scaled by a feedback coefficient 54) at summing circuit 44. The result is stored in the flip-flop circuit 46 and provided as an output 48 on pulses of a clock signal 50. The output 48 may then be additively combined with feed forward components of the equalized signal.